The present invention relates to the field of programmable devices, and the systems and methods for programming the same. Programmable devices, such as FPGAs, typically includes thousands of programmable logic cells that use either a combination of logic gates or a look-up table to perform a logic operation. Programmable devices also include a number of functional blocks having specialized logic devices adapted to a specific logic operations. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
A typical design cycle for determining the configuration of a programmable device starts with an extraction phase, followed by a logic synthesis phase, a fitting phase, and an assembly phase. The extraction phase takes a user design, typically expressed as a netlist in a hardware description language such as verilog or VHDL, and produces a set of logic gates implementing the user design. In the logic synthesis phase, the set of logic gates is permutated over the hardware architecture of the programmable device in order to match elements of the user design with corresponding portions of the programmable device. The fitting or routing phase assigns the various portions of the user design to specific logic cells and functional blocks of the programmable device, taking care to satisfy the user timing constraints as much as possible. In the assembly phase, a configuration file defining the programmable device configuration is created. The configuration can then be loaded into a programmable device to implement the user design.
Typically, the logic synthesis phase optimizes the netlist describing a user design to minimize the usage of the programmable device hardware, for example the number logic cells or functional blocks. By minimizing the usage of programmable device hardware, referred to generally as area, the design can be implemented using the simplest and presumably least expensive programmable device. However, minimizing the area of a user design tends to create data paths that pass through a large number of logic cells and/or functional blocks. This in turn increases the delay on data paths and decreases the maximum operating speed of the user design.
Alternatively, some logic synthesis methods optimize strictly for maximum operating speed. Unfortunately, these methods substantially increase the area requirements for a user design. As a result, the cost to implement the speed-optimized user design also increases. Furthermore, many speed optimization techniques increase area so much that the performance improvements gained from using additional programmable device hardware are negated by the additional path-induced delays introduced by the increased area of the design. Thus, the actual speed increase from these methods often falls short of theoretical projections.
It is therefore desirable for a logic synthesis method to provide improved design performance without a substantial increase in design area. It is further desirable that a logic synthesis method enables users to select whether a design should be optimized for improved speed, decreased area, or a balance of these two goals.